Questa® Connectivity Check

Questa Connectivity Check icon

Exhaustive,rapid verification of static and dynamic IP & SoC connectivity

Questa Connectivity Check应用程序是一个完全自动化的解决方案,可根据明文csv或ip-xact规范彻底验证静态和动态连接。No knowledge of formal or property specification languages is required.

The Idyllic Past vs.现代现实

回到今天,一个渴望合作的学生或者一个非常细心的发布工程师可以手动检查DUT的示意图,RTL code,and device spec for any connectivity discrepancies.Theoretically,today with modern"correct by construction"code generation tools and some basic linting,在SOC中验证IP之间的连接应该是一项微不足道的任务。In reality,even small SoCs can have tens of thousands of static and dynamic interconnections due to BIST,low power isolation circuitry,and multiplexing of I/O's layered on top of the baseline point-to-point IP interconnections.Even worse,在项目的整个生命周期中,不断地添加错误修复和ECO流,and connectivity verification has become a high risk,high cost testbench creation & debug project requiring weeks of man-hours and simulations all its own.

The Questa Connectivity Check app takes your RTL and connectivity spec as input,and automates formal technology to exhaustively verify all types of SoC interconnections.No knowledge of formal or property specification languages is required.

The Solution: Questa Connectivity Check

Using a cleartext,人机可读的电子表格和RTL作为输入,Questa Connectivity Check应用程序自动使用正式技术来彻底验证所有类型的静态和动态连接。Specifically,the app automatically derives all the required assertions from your CSV,IP-XACT,or XML connectivity spec.为了加快分析和/或最小化正式编译和运行时间,您的RTL中的IP内部区域是“blackboxed"to the keep focus on the connectivity alone.The result: even for the largest,most complex SoC's,exhaustive verification of all static and dynamic connections is completed by the formal engines within a matter of hours vs.基于试验台模拟方法所需的周数。


  • Verifies on-chip bus,inter-block,control signal,clock and reset connections at the sub-system or SoC level
  • Captures connectivity specifications in an easy-to-understand tabular format
  • Exhaustively checks all modes of operation


  • Completes exhaustive verification of all static and dynamic connections within a matter of hours
  • Very easy to setup – no knowledge of formal or assertions is required
  • Any mismatches between the spec and DUT are clearly defined by counterexample waveform(s) right at the mismatched interconnect point(s)
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