Questa® Power Aware Simulator

Verify active power management

The Questa® Power Aware Simulator enables design teams to verify the architecture and behavior of active power management planned for the implementation,but starting much earlier in the design process.

Verification of active power management at theRTL阶段使得在实施之前很早就可以探索替代电力管理方法,以最少的成本实现最大的功率降低。

后合成中有功功率管理的验证门级netlist stages makes it possible to ensure that synthesis and manual transformations have correctly preserved the active power management architecture and its behavior.

Power management has become a critical aspect of electronic systems design.Driven by customer demand for more functionality and longer battery life in portable electronics,and enabled by advances in process...




  • 将HDL设计划分为电源域,,
  • adds isolation,level-shifting,and retention cells,and
  • integrates the power supply network into the design to power each domain

The augmented HDL design can then be simulated with full control over the power state of each domain,for accurate modeling of the effects of active power management on the design's functionality.

Automatic Detection of Power Management Errors

The Questa Power Aware Simulator automatically detects power management errors in both the architecture and the behavior of the power management system.Static checks during compilation of the UPF identify architectural issues such as missing isolation or level-shifting cells.Dynamic checks during simulation identify behavioral issues such as incorrect control sequencing for powering up or powering down portions of the design.可以单独启用或禁用所有检查,以配置给定设计的适当检查集。

Automatic power management error checks include checks such as the following:

  • Level shifters and Isolation cells present where needed
  • 断电前保存的保留寄存器
  • 锁存启用在发生保持时正确设置
  • Clock is disabled during power down
  • Isolation is enabled during power down
  • 断电时输入不切换
  • 断电时保持/隔离电源开启且稳定
  • Primary power is on and stable during power up
  • Non-retention registers are reset at power up
  • 电源控制信号没有故障
  • Dynamic voltage changes are correctly mediated by level shifters


有功功率管理对设计结构和行为的影响体现在波形图中,the schematic view,and the power state/transition view.The waveform view highlights signals that have been corrupted due to powering down,以及为避免腐败而隔离的信号。The schematic view color codes design elements to indicate the power domain to which they belong.电源状态/转换视图显示系统及其每个电源域的当前电源状态,and the most recent power state transition,在类似于FSM的形式和类似于UPF电源状态表的表格形式中。


Power states and transitions are recorded in Mentor's Unified Coverage DataBase (UCDB) for integration with verification planning and management.这使得能够将功率感知的模拟目标纳入验证计划中,以便跟踪覆盖范围的关闭。

Chatγ Contact