Why do designers wait until very late in the design process to optimize power??

事实是,这不是他们的错。通常,在后台进程中,电源由特殊的组进行优化。In order to perform realistic systemic power optimization at the designers level,需要两件事:

  • 模拟性能比RTL模拟快一个数量级,以实现有效的勘探过程。
  • 高设计水平下的性能和功率精确建模
Why should we care about power at the design and architecture levels??

现在很明显,在体系结构级别,when you define your processors,公共汽车,记忆和集成软件,you have the greatest impact on power.一旦你的架构完成,你真正影响力量的空间要小得多。

Another key aspect is that power and performance are tightly coupled and impact each other.在体系结构级别,您可以看到系统性能,并且可以优化电源,同时确保性能也满足需求。


Although there is no standard way,users can use various methods to model and instrument power at the design and architecture levels.However,if the estimates are far off any realistic numbers,the whole analysis and optimization process may be meaningless.For any realistic exploration process,power data should be closely related to the actual physical numbers,至少对于大多数系统块。

Can we use statistic techniques at the TLM level to analyze power??

Yes,在各种情况下,您可以在统计流量条件下探索架构备选方案。在这种情况下,您还可以分析和平衡能力与性能。However,在许多情况下,在诸如软件应用程序执行这样的实际使用情况下,可以更好地优化电源。In such cases power should be testes under functional simulation.



How does incorporating power management techniques in my design introduce functional verification challenges??

低功耗架构的实现必须与硬件的实际行为相一致。例如,必须保留和恢复状态数据,ports must be isolated to prevent leakage and to clamp a safe logic value,而多电压系统需要电平转换,使逻辑值从一个电压域转换到另一个电压域。Historically,低功耗设计的功能影响验证在过程的后期(通常是在物理设计之后)进行,因为所有相关信息都不能很快以可验证的格式提供。Thus,low power design verification has been burdened with all the issues of full-timing,gate-level simulation: slow simulations with long turn-around times,long debug identification,分辨率高。Additionally,低功耗设计通常涉及多种格式,用于捕获各种低功耗意图和实现,resulting in inconsistent and contradictory specifications.



The implementation of retention registers changes from technology process node to another.How do I ensure that my power sequencing that was implemented for 65nm will continue to work with 45nm retention cells??

Through accurate behavioral modeling of retention functionality,power-aware RTL simulation can verify that the power control sequencing is correct for the target technology.例如,如果重置与恢复同时激活,保留模型将确保寄存器被重置或恢复,与该技术的保留寄存器的行为相匹配。

We have memory models that are power aware – retaining their contents when the core supply is on when the read/write logic is powered down.We also have ROM models that are not power aware.Can we verify our design including UPF for the synthesizable logic and using our existing RAM and ROM models??

Yes,你可以。ROMs can be recognized by their initialization.When power to the ROM is shutdown,内容无法读取。当电源恢复时,ROM的状态保持不变。电源感知RAM模型可以连接到在UPF中创建的电源网络,并且支持RAM模型的电源感知行为。




IC Implementation

How does MCMM optimization reduce overall power consumption??



路由引擎需要遵守已创建的不同电压岛。对应于一个域的路由应包含在同一域中。The routing engine also needs to ensure that the secondary power taps for the level shifters,开关单元和保持触发器处理得当。辅助抽头还应支持非默认路由规则,以最小化IR下降。

How does Olympus-SoC ensure minimum leakage power during physical design??

Olympus-SoC employs different techniques to optimize leakage power including Multi-vt libraries during optimization and also power gating using MTCMOS switches.在所有优化步骤中,泄漏被认为是一个成本函数和时间安排,这将导致更好的质量比。


时钟树构建过程中的功率优化可以通过许多不同的方式实现,包括更好的平衡时钟树网络以及树的最佳缓冲/反相器计数。Minimizing capacitance on the network via clustering of the flops also significantly helps minimize switching power.Clock gating is a common technique that is very effective to optimize dynamic power but care must be taken during placement of the clock gates such that timing is not affected.


dvfs是多vdd方法的一个扩展,它使用MCMM体系结构进行优化。用户通常会定义电压-频率对,这将成为一个MC优化问题。Multi-VDD methodology provides the infrastructure to define DVFS requirements and MCMM architecture helps realize the same.


用户将使用UPF语法定义Power域。UPF语法的一部分是为每个电源域指定默认的电源网络。UPF语法还将电压映射到设计中的电网:pst。When the timer times a cell it will check the vdd pin of the cell,找到连接到管脚的网络,通过PST,定时器就能知道电池上的电压。The timer then picks the library with the nominal voltage closes to the vdd on the leaf cell.

如果我有一个RAM或宏,其中有多个VDD管脚,how does the user specify which outputs are associated with each voltage??


如何使用Olympus SOC进行级别转换设置和插入??

电平移位器推断是使用UPF文件完成的。用户将定义意图,例如电平移位器需要驻留的域,二次电源连接,enable control etc is captured in the UPF file.Olympus SOC使用来自UPF文件的信息,并继续插入和放置电平移位器。

How does Olympus-SoC handle repeaters between voltage islands??

There are two options that can be used to handle repeaters: 1) using always-on buffers on the long nets 2) creating mini islands called gas stations to buffer the long nets between islands.