IC实施

Automatic Place & Route for Low Power Styles

Mentor Graphic的Olympus SoC Place and Route解决方案符合UPF标准,在放置期间处理各种低功耗设计风格,路由,and optimization.通过手动创建放置或路由,避免在设计周期中插入更多风险。”keep-out"areas,or trying to manually insert always-on buffers or isolation cells.

Olympus-SoC automates insertion of special cells,处理二次电源连接的路由,and respects power domain boundaries and connectivity.

Save Power in your Clock Tree

Clocks are the single largest source of dynamic power usage,时钟树综合优化是物理设计中实现显著节能的好地方。

Low-powerclock tree synthesis (CTS) strategiesinclude lowering overall capacitance,提高时钟选通覆盖率,减少开关活动。然而,从CTS获得最佳的功率结果取决于同时合成多个角和模式的时钟的能力。

Mentor's unique MCMM-based clock synthesis and optimization分析触发器交互to derive the skew balancing requirements across all corners concurrently.这就大大改善了歪斜,面积,and power in a single CTS run.

同时进行MCMM协同优化的闭合置信度

A key dimension to low power implementation ismanaging the complexityinherent in today's deep submicron designs.一个典型的低功耗集成电路可以有3个或更多的电源状态,例如待机,活跃的,and Sleep—plus a growing number of corners and modes,each of which can have conflicting requirements for timing,signal integrity (SI),manufacturability,和权力。

MCMM makes a difference当控制电源使用时-因为在高级进程节点上,lithography,process,操作的可变性以复杂的方式影响不同模式/角落场景中的功率。Variations in resistance due to uneven wire widths or CMP dishing can cause different results in one mode/corner scenario versus another.

Approximations,such as merging constraints from multiple process corners,can result in significant loss of accuracy,这使得关闭变得困难。With Mentor's solution,,all optimizations are concurrently appliedto all mode/corner scenarios so you get the best quality of results while reducing guard-banding that lowers the bar on performance.这意味着你得到了更低的功率和更高的性能,giving your ICs the edge over the competition.

大型设计的最大工具容量

Olympus-SoC has the highest capacity of any place and route system so you can perform full-chip power,IR液滴设计的电磁分析1亿门or more,在平面或层次模式下。You are never forced to segment designs and manually merge them because of your tool's limitations.

奥林巴斯SOC

The Olympus-SoC place and route system读取相同的UPF文件you used in system design and verification,因此,权力意图是通过实施来实现的。It supports advanced low power design techniques,包括多电源,power-shutoff,电压和频率比例。

The Olympus-SoCclock tree synthesis technology是业界首款多角CTS引擎。It produces very low power,高度优化的时钟树,通过分析触发器的交互作用,同时得出所有角的歪斜平衡要求。

The Olympus-SoC路由器处理所有二次电源连接以保持触发器和始终处于缓冲区。It respects voltage island boundaries and changes routing topology to meet other design constraints.For example,路由器绕岛绕行以缓冲非关键网络上的信号完整性(SI)冲突,但允许关键网跨越一个岛屿。要做到这一点,它依赖于对MCM定时和RC的不断更新来找到所有关键设计约束的最优解。

The router isvariability-awareso it accounts for the manufacturing issues that affect power,especially leakage power.Without concurrent MCMM leakage and timing optimization,you may never be able to resolve conflicting needs across different mode/corner combinations.

图像
Physical design flow for multi-voltage designs with MCMM.

Technical Tips

降低动态功率的一种越来越普遍的技术是multiple voltage islands(domains),which allow some blocks to use lower supply voltages than others,或在某些操作模式下完全关闭。This flow gets even more complex when dynamic voltage scaling is used to change the supply voltage level during operation.

Multi-voltage flows present new challenges in physical design.Firstly,the tools need to correctly place and route across multiple domains and ensure that the timing and optimization engines honor the multi-voltage domain specifications.Secondly,they need to ensure that the multi-mode multi-corner requirements are also satisfied in the same run.Basically,当考虑到所有最小/最大电压组合时,每个附加电压岛会使定时分析模式/转角方案的数量加倍。